This application claims the benefit of the Korean Application No. P2000-81182 filed on Dec. 23, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device in which capacitance between lines is reduced in a multi-layered line to improve reliability of the device.
2. Discussion of the Related Art
Recently, with high packing density of a semiconductor device, a device structure having a multi-layered line has been required. The distance between metal lines on the same layer has been gradually narrowed.
Parasitic resistance and parasitic capacitance existing between adjacent metal lines on the same layer or between adjacent metal lines in vertical direction have been highlighted.
Meanwhile, in fabricating a semiconductor device having ultra-high packing density, performance of a chip is limited by capacitance between lines as dimensions of the chip gradually become smaller.
In other words, capacitance between lines causes RC delay in fabricating a device, thereby degrading electrical characteristic of the device. Also, the capacitance between lines increases RC power consumption, and causes cross-talk, thereby increasing signal leakage.
Accordingly, to reduce capacitance between lines in a semiconductor device having ultra-high packing density, a metal line is formed using metal having low specific resistance or an insulating film having low dielectric constant is used.
Recently, an air gap is artificially formed between metal lines when an insulating interlayer is formed using step coverage of the metal line. Since the air gap has a dielectric constant of 1, a capacitance value can be reduced.
A related art method for fabricating a semiconductor device will be described with reference to FIGS. 1A to C.
FIGS. 1A to C are sectional views illustrating a related art method for fabricating a semiconductor device.
As shown in FIG. 1A, a conductive metal film is deposited on an interlayer dielectric 101 and selectively patterned by photolithography and etching processes, so that metal lines 102 are formed at a constant interval.
Oxide is used as a material of the interlayer dielectric 101.
As shown in FIG. 1B, oxide having low dielectric constant Low-K is deposited on an entire surface including the metal lines 102 by a plasma enhanced chemical vapor deposition (PECVD) method of poor step coverage, so that an intermetal dielectric 103 is formed.
When the intermetal dielectric 103 is formed, since the PECVD method of poor step coverage is used, an air gap 104 is formed between the metal lines 102 to reduce the capacitance.
As shown in FIG. 1C, a surface of the intermetal dielectric 103 is planarized by a chemical mechanical polishing (CMP) process. At this time, the air gap 104 formed in the intermetal dielectric 103 is exposed.
However, the related art method for fabricating a semiconductor device has several problems.
Since the air gap between the metal lines is exposed during the CMP process, short may be caused in a later process and capacitance between the lines cannot be reduced, thereby reducing reliability of the device.
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a semiconductor device in which an air gap is stably formed to reduce capacitance between lines, thereby improving reliability of the device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will become apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping layer to partially expose a surface of the interlayer dielectric to form a hole, selectively removing a side of the intermetal dielectric within the hole, depositing a metal film on an entire surface including the hole to form an air gap in a portion where the side of the intermetal dielectric is removed, and planarizing an entire surface of the metal film to expose a surface of the capping layer to form a plurality of metal lines.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.